1. Field of the Invention
The present invention relates to analog circuits that are applicable to communications systems, and more particularly, to an analog circuit that can improve response time by converting a signal having a low level, including zero, into a signal having a non-low level, set to be higher than a reference level, to thereby reduce a turn-on time delay (Td).
2. Description of the Related Art
Recently, research has been actively conducted into voltage-supply circuits and current-supply circuits using complementary metal-oxide-semiconductor (CMOS) technologies. Voltage followers are one of the most widely used circuits.
FIG. 1 is a circuit diagram illustrating a voltage follower according to the related art.
A voltage follower 10 according to the related art, shown in FIG. 1, is a buffer amplifier using an operational amplifier. The voltage follower 10 outputs an output voltage Vout from an input signal Vin without amplifying the level thereof.
The voltage follower 10 according to the related art causes a delay in an output voltage when an input voltage reaches zero voltage, and undergoes a drastic reduction in response time. That is, when the input voltage has a low level such as zero voltage, response time at the turn-on time of the voltage follower is markedly reduced.
FIG. 2 is a graph illustrating the response characteristics of the voltage follower of FIG. 1.
Referring to FIG. 2, in the voltage follower according to the related art, the response time of an amplifier of the voltage follower varies according to an input range of the input signal Vin.
In particular, when the amplifier is switched from an OFF-state to an ON-state, as shown in FIG. 2, the response time of the amplifier of the voltage follower is reduced to cause a time delay (Td). This delay, caused when the amplifier is turned on, adversely affects the operation of a circuit at a rear stage, thereby reducing the response time of the entire system.